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CY28551
.................... Document #: 001-05675 Rev. *C Page 11 of 28
4
0
R/W
WD_Alarm
WD_Alarm is set to ‘1’ when the watchdog times out. It is reset to ‘0’ when
the system clears the WD_TIMER time stamp
3
0
R/W
WD_TIMER2
Watchdog timer time stamp selection
000: Reserved (test mode)
001: 1 * Time_Scale
010: 2 * Time_Scale
011: 3 * Time_Scale
100: 4 * Time_Scale
101: 5 * Time_Scale
110: 6 * Time_Scale
111: 7 * Time_Scale
2
0
R/W
WD_TIMER1
1
0
R/W
WD_TIMER0
0
R/W
WD_EN
Watchdog timer enable. When the bit is asserted, Watchdog timer is
triggered and time stamp of WD_Timer is loaded
0 = Disable, 1 = Enable
Byte 13: Control Register 13
Bit
@Pup
Type
Name
Description
Byte 14: Control Register 14
Bit
@Pup
Type
Name
Description
7
0
R/W
CPU_DAF_N7
If Prog_CPU_EN is set, the values programmed in CPU_DAF_N[8:0] and
CPU_DAF_M[6:0] will be used to determine the CPU output frequency.
The setting of the FS_Override bit determines the frequency ratio for CPU
and other output clocks. When it is cleared, the same frequency ratio
stated in the Latched FS[E:A] register will be used. When it is set, the
frequency ratio stated in the FSEL[3:0] register will be used
6
0
R/W
CPU_DAF_N6
5
0
R/W
CPU_DAF_N5
4
0
R/W
CPU_DAF_N4
3
0
R/W
CPU_DAF_N3
2
0
R/W
CPU_DAF_N2
1
0
R/W
CPU_DAF_N1
0
R/W
CPU_DAF_N0
Byte 15: Control Register 15
Bit
@Pup
Type
Name
Description
7
0
R/W
CPU_DAF_N8
If Prog_CPU_EN is set, the values programmed in CPU_DAF_N[8:0] and
CPU_DAF_M[6:0] will be used to determine the CPU output frequency.
The setting of the FS_Override bit determines the frequency ratio for CPU
and other output clocks. When it is cleared, the same frequency ratio
stated in the Latched FS[E:A] register will be used. When it is set, the
frequency ratio stated in the FSEL[3:0] register will be used.
6
0
R/W
CPU_DAF_M6
5
0
R/W
CPU_DAF_M5
4
0
R/W
CPU_DAF_M4
3
0
R/W
CPU_DAF_M3
2
0
R/W
CPU_DAF_M2
1
0
R/W
CPU_DAF_M1
0
R/W
CPU_DAF_M0
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